1. Field of the Invention
One or more embodiments relate to a flash memory device and a method of manufacturing the same and, more particularly, to a flash memory device and a method of manufacturing the same, which are capable of increasing the area of an active region and improving a bend phenomenon of the active region.
2. Brief Description of Related Technology
The memory cell array of a flash memory device includes string structures arranged in a matrix form. Each of the string structures includes a drain select transistor having a drain coupled to a bit line, a source select transistor having a source coupled to a common source line, and a number of memory cells coupled in series between the drain select transistor and the source select transistor. The string structures are electrically isolated from each other by an isolation structure interposed therebetween. Gates of the string structures are arranged in parallel and are coupled to form gate lines. The gate lines include a drain select line to which the gates of the drain select transistors are coupled, a source select line to which the gates of the source select transistors are coupled, and word lines to each of which the gates of the memory cells are coupled. Such gate lines are formed by coupling the drain select transistor, the source select transistor, and the control gates of stacked gates included in the memory cells. The stacked gate has a stack structure of a floating gate, a dielectric layer, and the control gate.
Junctions are formed in the active regions of a semiconductor substrate defined on both sides of the gate. The active regions are defined by etching the semiconductor substrate to thus form trenches, and forming the isolation structures within the respective trenches. That is, the isolation structures are not formed in the active regions of the semiconductor substrate. Furthermore, the junctions include a cell junction, a source region, and a drain region. The memory cell gates within the same string structure are coupled through the cell junction, the gates of the source select transistors are coupled through the source region, and the gates of the drain select transistors are coupled through the drain region. Here, the source region and the drain region couple the unit string structures arranged in a line in the direction of the string. Further, the source regions arranged in parallel are coupled to a source contact line of a line form.
FIG. 1 is a layout diagram showing the active regions and the isolation regions of a known flash memory device.
Referring to FIG. 1, as described above, the string structures arranged in a line are coupled with the junction interposed therebetween, and the parallel string structures are isolated from each other with the isolation structure 3 interposed therebetween. To this end, in the cell region of the flash memory device, the isolation structures 3 and the active regions 5a are alternately defined in parallel, and each are lengthily defined in one direction without disconnection.
Meanwhile, the gate lines are formed to intersect the isolation structures 3 and the active regions 5a which are lengthily defined in one direction. The gate lines include the word lines WL to each of which the gates of the memory cells are coupled and the source select lines SSL to each of which the gates of the source select transistors are coupled. The source region is formed in the active region 5a between the source select lines SSL and is coupled to a source contact line SCT. Here, the area of the source region with which the source contact line SCT comes into contact is narrowed with semiconductor devices high integrated.
FIGS. 2A and 2B illustrate problems resulting from a reduction in the area of the source region.
Referring to FIG. 2A, when evaluating a probe test (PT) for testing reliability of a flash memory chip, if the chip has a good state, a drain current (Id) having a reference value or more must flow between the source and the drain in the flash memory chip of an erase state. That is, if the drain current (Id) is less than the reference value, the chip is determined to be a fail. Such a fail is caused by an increase in the contact resistance (Rc) of the source contact line and the source region according to a reduction in the area of the source region because of the high integration of semiconductor devices.
Referring to FIG. 2B, the contact resistance (Rc) of the source contact line and the source region can be further increased by the influence of oxide 15 which is locally formed between the junction of a semiconductor substrate and conductive layers 17, 15 constituting a source contact plug. Here, the oxide 15 may be formed between the barrier metal 15 and the junction in a process of forming a source contact hole by etching a dielectric interlayer protecting a gate line 11 and then forming the barrier metal 15. Influence of an alien substance, such as the oxide 15 formed at the interface of the source contact line and the source region in the process of manufacturing the flash memory device, on the performance of a device is increased with a reduction in the area of the active region.
FIG. 3 illustrates a problem resulting from a narrowed active region.
Referring to FIG. 3, with the high integration of semiconductor devices, the width of the active region 5a is much narrowed as compared to the height of the active region 5a. Furthermore, the active regions 5a are lengthily formed in one direction, as described above with reference to FIG. 1. Accordingly, the active regions 5a are vulnerable to external shock and stress, such as heat generated in subsequent processes, and so prone to bend as shown in a region A.